Computer Science

Architecture

Build faster and more power-efficient computers using demand-driven computing. Find alternative methods to build and program processors. Our research focuses on development of demand-driven execution, an alternate execution paradigm for processor architecture and programming model in which execution proceeds from outputs toward inputs, extracting and mapping—research leading to a new era of parallel computing. We break down the barriers of how the programs are represented and executed to come up with extremely scalable architectures.

"Existing processors have hit a plateau. We cannot improve their performance any further. The only solution appears to be using parallelism."Soner Onder, professor of computer science

Current Project

Project Title: SPHINX: Combining Data and Instruction Level Parallelism through Demand Driven Execution of Control Flow Programs

Investigator: Soner Onder

Sponsor: National Science Foundation

Overview: It has become increasingly difficult to improve the performance of processors so that they can meet the demands of existing and emerging workloads. Recent emphasis has been towards enhancing the performance through the use of multi-core processors and Graphics Processing Units. However, these processors remain difficult to program and inflexible to adapt to dynamic changes in the available parallelism in a given program. Although the computer architecture and programming language community continues to innovate and make important gains towards better programmability and better designs, it remains that parallel programming is inherently costly and error prone, and automatic parallelization of programs is not always feasible or effective. The intellectual merits of this project are the development of a new program execution paradigm and the establishment of critical compiler and micro-architecture mechanisms so that one can design processors that can be easily programmed using existing programming languages and at the same time surpass the performance of existing parallel computers. The project's broader significance and importance are wide-spread: the deployment of such processors will push the limits of computation in every field of science and commerce.


Project Title: Foundational Microarchitecture Research : Dependent ILP: Dynamic Hoisting and Eager Scheduling of Dependent Instructions

Investigator: Soner Onder

Sponsor: National Science Foundation

Instruction-level parallelism (ILP) in computing allows different machine-level instructions within an application to execute in parallel within a micro-processor. Exploitation of ILP has provided significant performance benefits in computing, but there has been little improvement in ILP in recent years. This project proposes a new approach called "eager execution" that could significantly increase ILP. The success of many applications depends on how efficiently they can be executed. The proposed eager execution technique will benefit applications that span those running on mobile devices to large data applications running on the ever-growing number of data centers. Enabling better systems at all scales will further enable the ubiquitous computing that continues to pervade lives.

The project's approach includes the following advantages: (1) immediately-dependent consumer instructions can be more quickly delivered to functional units for execution; (2) the execution of instructions whose source register values have not changed since its last execution can be detected and redundant computation can be avoided; (3) the dependency between a producer/consumer pair of instructions can sometimes be collapsed so they can be simultaneously dispatched for execution; (4) consumer instructions from multiple paths may be speculatively executed and their results can be naturally retained in the paradigm to avoid re-execution after a branch misprediction; and (5) critical instructions can be eagerly executed to improve performance, which include loads to prefetch cache lines and pre-computation of branch results to avoid branch misprediction delays. 


Researchers

Saeid Nooshabadi

  • Professor, Electrical and Computer Engineering
  • Professor, Computer Science

Area of Expertise (CS)

  • High-performance computer architecture
  • Embedded systems
  • Design of multimedia systems
  • High-performance and low power computing systems
  • Information-processing systems
  • Embedded electronic systems

Areas of Interest (ECE)

  • VLSI information and multimedia processing
  • SoC design
  • Complex embedded electronic systems
  • Very Large Scale Intergradations (VLSI)
  • Digital architectures
  • Computer engineering

Soner Onder

  • Professor, Computer Science
  • Affiliated Professor, Electrical and Computer Engineering

Area of Expertise

  • Computer Architecture
  • Programming Languages
  • Simulation

Zhenlin Wang

  • Interim Department Chair, Computer Science
  • Professor, Computer Science

Links of Interest

Area of Expertise

  • Optimizing Compilers
  • High Performance Architectures
  • Cloud Computing

Jianhui Yue

  • Assistant Professor, Computer Science

Links of Interest

Areas of Expertise

  • Computer Architecture
  • Operating System
  • System Optimization of Big Data Process

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