Saeid Nooshabadi

Saeid Nooshabadi

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Professor, Electrical and Computer Engineering

Professor, Computer Science

  • PhD, Integrated Circuits (VLSI), Indian Institute of Technology Delhi (IITD)
  • MTech, Integrated Circuits (VLSI), Indian Institute of Technology Delhi (IITD)
  • MS, Nuclear Instrumentation, Andhra University, India
  • BS, Physics, Andhra Uni., India

Biography

Saeid Nooshabadi has a joint appointment as a professor in high-performance computer architecture, embedded systems and VLSI signal processing in the Department of Electrical and Computer Engineering and the Department of Computer Science at Michigan Technological University. Prior to his current appointment, he was a professor in VLSI multimedia signal processing in the Department of Information and Communications at the Gwangju Institute of Science and Technology, in the Republic of Korea. In 1992, Nooshabadi was a research scientist at the CAD Laboratory, of the Indian Institute of Science in Bangalore, working on the design of VLSI chips for TV ghost cancellation in digital TV. In 1996 and 1997, he was a visiting faculty member and researcher at the Center for Very High Speed Microelectronic Systems, of Edith Cowan University in Western Australia, working on high performance integrated circuits; and at Curtin University of Technology, in Western Australia, working on the design of high speed–high frequency modems. From 2000 to 2007 he was with the School of Electrical Engineering and Telecommunications at the University of New South Wales, in Sydney, where he currently holds an adjunct appointment.

Nooshabadi has extensive research and teaching experience and interests in the area of SoC design of multimedia systems, high-performance and low-power computing systems, application-specified integrated circuit design for information-processing systems, and embedded electronic systems. He is coauthor of multiple patents and more than 150 technical journal and conference papers on all aspects of VLSI information processing. He has supervised more than twenty postgraduate students.

He is a coauthor on papers that received the best paper award for the 2007 Midwest Conference on Circuits and Systems and the 1997 VLSI Design Conference.

Nooshabadi received an MTech and a PhD in Electrical Engineering from the India Institute of Technology, Delhi, in 1986 and 1992, respectively.

Area of Expertise (CS)

  • High-performance computer architecture
  • Embedded systems
  • Design of multimedia systems
  • High-performance and low power computing systems
  • Information-processing systems
  • Embedded electronic systems

Areas of Interest (ECE)

  • VLSI information and multimedia processing
  • SoC design
  • Complex embedded electronic systems
  • Very Large Scale Intergradations (VLSI)
  • Digital architectures
  • Computer engineering

Recent Publications

  • T Mladenov, S. Nooshabadi,, and K. Kim, “MBMS Raptor Codes Design Trade-offs for IPTV”, IEEE Transactions on Consumer Electronics, vol. 56, no. 3, pp. xxx, August 2010.
  • T. Mladenov, S. Nooshabadi, and K. Kim, “Implementation and Evaluation of Raptor Codes on Embedded Systems”, Accepted for IEEE Transactions on Computers, vol. 59, no. x, pp. xxx, xxx 2010. (Accepted Aug. 2010)
  • F. Sobhanmanesh, S. Nooshabadi, and E. Aboutanios, “An efficient VLSI architecture for 4 × 4 16-QAM sorted QR-factorisation based V-BLAST decoder”, International Journal of Electronics and Communications, In Press, Corrected Proof, Available online 10 July 2010, doi:10.1016/j.aeue.2010.06.002.
  • T Mladenov, S. Nooshabadi,, and K. Kim, “Strategies for the Design of Raptor Decoding in Broadcast/Multicast Delivery Systems”, IEEE Transactions on Consumer Electronics, vol. 56, no. 2, pp. 423-428, May 2010.
  • J. Sosa, S. Nooshabadi, and J. A. Montiel–Nelson, “Application of mixed integer linear programming in the generation of vectors with maximum datapath coverage for combinational logic circuits”, Journal of Circuits, Systems, and Computers, vol. 19, no. 7, pp. 1 – 22, July 2010.
  • J. Sosa, S. Nooshabadi, and J. A. Montiel–Nelson, “A genetic algorithm methodology to find the maximum datapath coverage for combinational logic circuits”, Journal of Circuits, Systems, and Computers, vol 19. no 2, pp., 435-450, Apr 2010.
  • Chul Kim, and S. Nooshabadi, “Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Nanoendescope”, IEEE Transactions on Biomedical Circuits and Systems, vol.4, no. 2, pp. 118 - 124, Apr. 2010.
  • J. Sosa, S. Nooshabadi, and J. A. Montiel–Nelson, “Application of Genetic Algorithm in Computing the Tradeoffs between Power Consumption versus Delay in Digital Integrated Circuit Design”, Microelectronics Journal, vol. 41, no. 2-3, pp. 135-141, Feb.-Mar. 2010.
  • D. H. Lee, S. Nooshabadi, and K. Kim, “Dual-mode SM/STBC System with Antenna Subset Selection employing ML Detection”, International Journal of Electronics and Communications, In Press, Corrected Proof, Available online 8 December 2009, doi:10.1016/j.aeue.2009.11.006.
  • J. C. García, S. Nooshabadi, and J. A. Montiel–Nelson “CMOS design and analysis of low-voltage signalling methodology for energy efficient on-chip interconnects”, Microelectronic Journal, vol. 40, no. 11, pp. 1571-1581, Nov. 2009.
  • J. C. García, J. A. Montiel–Nelson and S. Nooshabadi, “On the Design and Optimization of Symmetric Low Swing to High Swing Level Converter for on-Chip Interconnects”, Journal of analog integrated circuits and signal processing, vol. 60, nos. 1-2, pp. 35-42, August 2009.
  • S. Zezza, S. Nooshabadi, M. Martina, and G. Masera, “Efficient Implementation Techniques for ML Based Error Correction for JPEG2000”, IEEE Trans. on Circuits and Systems for Video Technology, vol. 19, no. 4, pp 591-596, April 2009.
  • H. Navarro, S. Nooshabadi, and J. A. Montiel–Nelson, “An adder model for mixed integer linear programming,” IEE Electronics Letters, vol. 45, no. 7, pp, 348-349, 26 March 2009.
  • M. Dyer, S. Nooshabadi, D. Taubman, “Design and Analysis of System on a Chip Encoder for JPEG2000”, IEEE Trans. on Circuits and Systems for Video Technology, vol. 19, no. 2, pp 215-225, Feb 2009.
  • J. C. García, J. A. Montiel–Nelson and S. Nooshabadi, “CMOS Driver--Receiver Pair for Low--Swing Signaling for Low Energy On—Chip Interconnects”, IEEE Trans. On VLSI Systems, vol. 17, no. 2, pp. 311 - 316, Feb. 2009.

Recent Funding

  • Grant from Korean Science Foundation, Korea, for the project "embedded system design for Multi dimensional signal processing"
  • Grant from Korean Science Foundation, Korea, for the project "Nano Scale Circuit Design Methodology"
  • Grant from US National Science Foundation for the project "Wireless Location Positioning System"
  • Grant from Electronic and Telecommunication Research Institute (ETRI), Korea, for the project "Multi-User MIMO Design"
  • Australian Research Council Linkage Infrastructure, Equipment, and Facilities (LIFE), a linkage grant between three Australian universities, for the "Development of 4G wireless communication systems and wireless sensor networks"
  • Australian Research Council Discovery grant for (in 20% top funding range) for "Reliable Truly Deep Sub-micron VLSI Computational Systems"
  • Australian Research Council Discovery Faculty Research Grant for "Digital Hardware Design of a DNA Sequence Pattern Matching"