Shiyan Hu

Shiyan Hu


Associate Professor, Electrical and Computer Engineering

  • PhD, Computer Engineering, Texas A&M University
  • MS, Computer Science, Polytechnic University
  • BS, Computer Science, Beijing University of Aeronautics & Astron


Shiyan Hu received his PhD in Computer Engineering from Texas A&M University. In 2007, he spent seven months in the IBM Austin Research Lab, working on VLSI Physical Synthesis. He is currently an assistant professor in the Department of Electrical and Computer Engineering at Michigan Tech. Hu’s research interests are in the area of computer-aided design of VLSI circuits and combinatorial optimizations. He has published over forty technical papers in referred journals and conferences, including IEEE Transactions on CAD, IEEE Transactions on VLSI, IEEE Transactions on CAS-II, and IEEE/ACM DAC, IEEE/ACM ICCAD, ACM ISPD. He is an associate editor for the Journal of Circuits, Systems and Signal Processing (Springer/Birkhauser) and the International Journal of Electronics and Communications (Elsevier). Hu has served as the Technical Program Committee (TPC) member for various conferences, including ICCAD, ISQED, SOCC, ISVLSI, and ISCAS. Currently, he is the director of the Michigan Tech VLSI CAD Research Lab.

Areas of Interest

  • Computer-aided design of VLSI circuits and combinatorial optimizations

Recent Publications

  • Jiang Hu, Zhuo Li, Shiyan Hu, Buffer Insertion: Basics, in the Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, ed., November, 2008. (invited)
  • Shiyan Hu, Mahesh Ketkar and Jiang Hu, Gate Sizing For Cell Library-Based Designs, IEEE Transactions on Computer-Aided Design (TCAD), Vol. 28, No. 6, pp. 818-825, June, 2009.
  • Xiaodao Chen, Chen Liao, Tongquan Wei, Shiyan Hu, An Interconnect Reliability-Driven Routing Technique For Electromigration Failure Avoidance, accepted to IEEE Transactions on Dependable and Secure Computing (TDSC).
  • Shiyan Hu, Pratik Shah and Jiang Hu, Pattern Sensitive Placement Perturbation For Manufacturability, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18, No. 6, pp. 1002-1006, June, 2010.
  • Shiyan Hu, Zhuo Li, Charles J. Alpert, A Fully Polynomial Time Approximation Scheme For Timing Constrained Minimum Cost Layer Assignment, IEEE Transactions on Circuits and Systems - II (TCAS-II), Vol. 56, No. 7, pp. 580-584, July, 2009.
  • Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang Karandikar, Zhuo Li, Weiping Shi and C. N. Sze, Fast Algorithms for Slew Constrained Minimum Cost Buffering, IEEE Transactions on Computer-Aided Design (TCAD), Vol. 26, No. 11, pp. 2009-2022, November, 2007.
  • Shiyan Hu, Qiuyang Li, Jiang Hu and Peng Li, Utilizing Redundancy for Timing Critical Interconnect, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15, No. 10, pp. 1067-1080, October, 2007.